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Features
* Utilizes the AVR(R) RISC Architecture * AVR - High-performance and Low-power RISC Architecture
- 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 20 MIPS Throughput at 20 MHz Data and Non-volatile Program and Data Memories - 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles - 128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - 128 Bytes Internal SRAM - Programming Lock for Flash Program and EEPROM Data Security Peripheral Features - One 8-bit Timer/Counter with Separate Prescaler and Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes - Four PWM Channels - On-chip Analog Comparator - Programmable Watchdog Timer with On-chip Oscillator - USI - Universal Serial Interface - Full Duplex USART Special Microcontroller Features - debugWIRE On-chip Debugging - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Low-power Idle, Power-down, and Standby Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator I/O and Packages - 18 Programmable I/O Lines - 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF Operating Voltages - 1.8 - 5.5V (ATtiny2313V) - 2.7 - 5.5V (ATtiny2313) Speed Grades - ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Typical Power Consumption - Active Mode 1 MHz, 1.8V: 230 A 32 kHz, 1.8V: 20 A (including oscillator) - Power-down Mode < 0.1 A at 1.8V
*
*
*
8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny2313/V Preliminary Summary
* * * *
Rev. 2543IS-AVR-04/06
Pin Configurations
Figure 1. Pinout ATtiny2313
PDIP/SOIC
(RESET/dW) PA2 (RXD) PD0 (TXD) PD1 (XTAL2) PA1 (XTAL1) PA0 (CKOUT/XCK/INT0) PD2 (INT1) PD3 (T0) PD4 (OC0B/T1) PD5 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC PB7 (UCSK/SCL/PCINT7) PB6 (MISO/DO/PCINT6) PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PB0 (AIN0/PCINT0) PD6 (ICP)
MLF
PB7 (UCSK/SCK/PCINT7) 17 PB6 (MISO/DO/PCINT6) 16
15 14 13 12 11
PA2 (RESET/dW) 19
PD0 (RXD)
20
(TXD) PD1 XTAL2) PA1 (XTAL1) PA0 (CKOUT/XCK/INT0) PD2 (INT1) PD3
1 2 3 4 5
18
VCC
PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1)
(T0) PD4
(OC0B/T1) PD5
NOTE: Bottom pad should be soldered to ground.
Overview
The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
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ATtiny2313/V
2543IS-AVR-04/06
(AIN0/PCINT0) PB0
(ICP) PD6
GND
10
6
7
8
9
ATtiny2313/V
Block Diagram
Figure 2. Block Diagram
XTAL1 PA0 - PA2
XTAL2
PORTA DRIVERS
VCC
DATA REGISTER PORTA
DATA DIR. REG. PORTA
INTERNAL CALIBRATED OSCILLATOR
8-BIT DATA BUS GND PROGRAM COUNTER STACK POINTER
INTERNAL OSCILLATOR
OSCILLATOR
WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER
TIMING AND CONTROL
RESET
PROGRAM FLASH
SRAM
ON-CHIP DEBUGGER
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTER
TIMER/ COUNTERS INTERRUPT UNIT
INSTRUCTION DECODER
EEPROM CONTROL LINES ALU USI STATUS REGISTER
PROGRAMMING LOGIC
SPI
USART
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD6
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2543IS-AVR-04/06
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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ATtiny2313/V
Pin Descriptions
VCC GND Port A (PA2..PA0) Digital supply voltage. Ground. Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313 as listed on page 53. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny2313 as listed on page 53. Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313 as listed on page 56. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1 is an alternate function for PA0. Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1. A comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.atmel.com/avr.
XTAL1
XTAL2
Resources
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Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (ox42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
SREG Reserved SPL OCR0B GIMSK EIFR TIMSK TIFR SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL Reserved CLKPR ICR1H ICR1L GTCCR TCCR1C WDTCSR PCMSK Reserved EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PORTD DDRD PIND USIDR USISR USICR UDR UCSRA UCSRB UBRRL ACSR Reserved Reserved Reserved Reserved UCSRC UBRRH DIDR Reserved
Bit 7
I - SP7 INT1 INTF1 TOIE1 TOV1 - PUD - FOC0A - COM0A1 COM1A1 ICNC1
Bit 6
T - SP6 INT0 INTF0 OCIE1A OCF1A - SM1 - FOC0B CAL6 COM0A0 COM1A0 ICES1
Bit 5
H - SP5 PCIE PCIF OCIE1B OCF1B - SE - - CAL5 COM0B1 COM1B1 -
Bit 4
S - SP4 - - - - CTPB SM0 - - CAL4 COM0B0 COM1BO WGM13
Bit 3
V - SP3 - - ICIE1 ICF1 RFLB ISC11 WDRF WGM02 CAL3 - - WGM12
Bit 2
N - SP2 - - OCIE0B OCF0B PGWRT ISC10 BORF CS02 CAL2 - - CS12
Bit 1
Z - SP1 - - TOIE0 TOV0 PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11 CS11
Bit 0
C - SP0 - - OCIE0A OCF0A SELFPRGEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10
Page
7 10 78 60 62 79, 110 79 156 78 53 37 77 78 25 74 105 108 109 109 109 109 110 110
Timer/Counter0 - Compare Register B
Timer/Counter0 - Compare Register A
Timer/Counter0 (8-bit)
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Compare Register A High Byte Timer/Counter1 - Compare Register A Low Byte Timer/Counter1 - Compare Register B High Byte Timer/Counter1 - Compare Register B Low Byte - CLKPCE - - - - - - - CLKPS3 - CLKPS2 - CLKPS1 - CLKPS0
27 110 110
Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte - FOC1A WDIF PCINT7 - - - - - - PORTB7 DDB7 PINB7 - - - - PORTB6 DDB6 PINB6 EEPM1 - - - PORTB5 DDB5 PINB5 EEPM0 - - - PORTB4 DDB4 PINB4 - FOC1B WDIE PCINT6 - - - WDP3 PCINT5 - - - WDCE PCINT4 - - - WDE PCINT3 - EEPROM Address Register EEPROM Data Register EERIE - - - PORTB3 DDB3 PINB3 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 - - WDP2 PCINT2 - - - WDP1 PCINT1 - PSR10 - WDP0 PCINT0 -
82 109 42 62 15 16 16 58 58 58 58 58 58 20 20 20
General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 - - - USISIF USISIE RXC RXCIE ACD - - - - - - - - PORTD6 DDD6 PIND6 USIOIF USIOIE TXC TXCIE ACBG - - - - UMSEL - - - PORTD5 DDD5 PIND5 USIPF USIWM1 UDRE UDRIE ACO - - - - UPM1 - - - PORTD4 DDD4 PIND4 USIDC USIWM0 FE RXEN ACI - - - - UPM0 - - - - - - - PORTD3 DDD3 PIND3 USICNT3 USICS1 DOR TXEN UBRRH[7:0] ACIE - - - - USBS PORTD2 DDD2 PIND2 USICNT2 USICS0 UPE UCSZ2 ACIC - - - - UCSZ1 UBRRH[11:8] AIN1D - AIN0D - PORTD1 DDD1 PIND1 USICNT1 USICLK U2X RXB8 ACIS1 - - - - UCSZ0 PORTD0 DDD0 PIND0 USICNT0 USITC MPCM TXB8 ACIS0 - - - - UCPOL
58 58 58 145 146 147 130 130 132 134 150
USI Data Register
UART Data Register (8-bit)
133 134 151
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ATtiny2313/V
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
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Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7)
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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ATtiny2313/V
Mnemonics
ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A
Operands
Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear
Description
Rotate Right Through Carry
Operation
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0
Flags
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
MCU CONTROL INSTRUCTIONS
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Ordering Information
Speed (MHz)(3) Power Supply Ordering Code ATtiny2313V-10PI ATtiny2313V-10PU(2) ATtiny2313V-10SI ATtiny2313V-10SU(2) ATtiny2313V-10MU(2) ATtiny2313-20PI ATTINY2313-20PU(2) ATtiny2313-20SI ATtiny2313-20SU(2) ATtiny2313-20MU(2) Package(1) 20P3 20P3 20S 20S 20M1 20P3 20P3 20S 20S 20M1 Operation Range
10
1.8 - 5.5V
Industrial (-40C to 85C)
20
2.7 - 5.5V
Industrial (-40C to 85C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 82 on page 181 and Figure 83 on page 181.
Package Type 20P3 20S 20M1 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)
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ATtiny2313/V
2543IS-AVR-04/06
ATtiny2313/V
Packaging Information
20P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 25.493 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 25.984 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
1/12/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C
R
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2543IS-AVR-04/06
20S
C
1
EH
N
Top View
A1
End View
COMMON DIMENSIONS (Unit of Measure = inches)
e
b A D
SYMBOL
MIN
L
NOM
MAX
NOTE
A A1 b C D
0.0926 0.0040 0.0130 0.0091 0.4961 0.2914 0.3940 0.0160 0.050 BSC
0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 0.4190 0.050 3 1 2 4
Side View
E H L e
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm 1/9/02 (0.024") per side.
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
DRAWING NO. 20S2
REV. A
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ATtiny2313/V
20M1
D
1 Pin 1 ID 2 3
E
SIDE VIEW
TOP VIEW A2 D2 A1 A
1 Pin #1 Notch (0.20 R) 2 3
0.08
C
E2
SYMBOL A A1
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 - NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE
b
L e BOTTOM VIEW
A2 b D D2 E E2 e
Note:
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
L
10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A
R
13
2543IS-AVR-04/06
Errata
ATtiny2313 Rev B
The revision in this section refers to the revision of the ATtiny2313 device. * * * *
Wrong values read after Erase Only operation Parallel Programming does not work Watchdog Timer Interrupt disabled EEPROM can not be written below 1.9 volts
1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. Parallel Programming does not work Parallel Programming is not functioning correctly. Because of this, reprogramming of the device is impossible if one of the following modes are selected: - - In-System Programming disabled (SPIEN unprogrammed) Reset Disabled (RSTDISBL programmed)
Problem Fix/Workaround Serial Programming is still working correctly. By avoiding the two modes above, the device can be reprogrammed serially. 3. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. 4. EEPROM can not be written below 1.9 volts Writing the EEPROM at VCC below 1.9 volts might fail. Problem fix / Workaround Do not write the EEPROM when VCC is below 1.9 volts.
ATtiny2313 Rev A
Revision A has not been sampled.
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ATtiny2313/V
Datasheet Revision History
Changes from Rev. 2514H-02/05 to Rev. 2514I-04/06
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
1. 2. 3 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
Updated typos. Updated Figure 1 on page 2. Added "Resources" on page 6. Updated "Default Clock Source" on page 25. Updated "128 kHz Internal Oscillator" on page 30. Updated "Power Management and Sleep Modes" on page 33 Updated Table 3 on page 25,Table 13 on page 33, Table 14 on page 34, Table 19 on page 45, Table 31 on page 63, Table 79 on page 180. Updated "External Interrupts" on page 62. Updated "Bit 7..0 - PCINT7..0: Pin Change Enable Mask 7..0" on page 65. Updated "Bit 6 - ACBG: Analog Comparator Bandgap Select" on page 153. Updated "Calibration Byte" on page 164. Updated "DC Characteristics" on page 181. Updated "Register Summary" on page 6. Updated "Ordering Information" on page 10. Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to OCF1x.
Changes from Rev. 2514G-10/04 to Rev. 2514H-02/05
1. 2. 3. 4. 5.
Updated Table 6 on page 24, Table 15 on page 34, Table 68 on page 161 and Table 80 on page 180. Changed CKSEL default value in "Default Clock Source" on page 22 to 8 MHz. Updated "Programming the Flash" on page 166, "Programming the EEPROM" on page 168 and "Enter Programming Mode" on page 164. Updated "DC Characteristics" on page 178. MLF option updated to "Quad Flat No-Lead/Micro Lead Frame (QFN/MLF)"
Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04
1. 2. 3. 4. 5.
Updated "Features" on page 1. Updated "Pinout ATtiny2313" on page 2. Updated "Ordering Information" on page 10. Updated "Packaging Information" on page 11. Updated "Errata" on page 14.
Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04
1. 2. 3.
Updated "Features" on page 1. Updated "Alternate Functions of Port B" on page 53. Updated "Calibration Byte" on page 161.
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2543IS-AVR-04/06
4. 5. 6. 7. 8. 9. 10.
Moved Table 69 on page 161 and Table 70 on page 162 to "Page Size" on page 161. Updated "Enter Programming Mode" on page 164. Updated "Serial Programming Algorithm" on page 174. Updated Table 78 on page 175. Updated "DC Characteristics" on page 178. Updated "ATtiny2313 Typical Characteristics" on page 182. Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and EEWE to EEPE in the document.
Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04
1.
2. 3. 4. 5.
Speed Grades changed - 12MHz to 10MHz - 24MHz to 20MHz Updated Figure 1 on page 2. Updated "Ordering Information" on page 10. Updated "Maximum Speed vs. VCC" on page 181. Updated "ATtiny2313 Typical Characteristics" on page 182.
Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04
1. 2. 3. 4. 5. 6. 7. 8. 9.
Updated Table 2 on page 22. Replaced "Watchdog Timer" on page 39. Added "Maximum Speed vs. VCC" on page 181. "Serial Programming Algorithm" on page 174 updated. Changed mA to A in preliminary Figure 136 on page 208. "Ordering Information" on page 10 updated. MLF package option removed Package drawing "20P3" on page 11 updated. Updated C-code examples. Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable.
Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03 Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03
1.
Updated "Calibrated Internal RC Oscillator" on page 24.
1. 2. 3. 4. 5. 6. 7. 8. 9.
Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in "Features" on page 1. Updated "Pin Configurations" on page 2. Updated Table 15 on page 34 and Table 80 on page 180. Updated item 5 in "Serial Programming Algorithm" on page 174. Updated "Electrical Characteristics" on page 178. Updated Figure 82 on page 181 and added Figure 83 on page 181. Changed SFIOR to GTCCR in "Register Summary" on page 6. Updated "Ordering Information" on page 10. Added new errata in "Errata" on page 14.
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